[ATE]am335x-evm.dts 20 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /dts-v1/;
  9. #include "am33xx.dtsi"
  10. #include <dt-bindings/interrupt-controller/irq.h>
  11. / {
  12. model = "TI AM335x EVM";
  13. compatible = "ti,am335x-evm", "ti,am33xx";
  14. chosen {
  15. stdout-path = &uart0;
  16. tick-timer = &timer2;
  17. };
  18. cpus {
  19. cpu@0 {
  20. cpu0-supply = <&vdd1_reg>;
  21. };
  22. };
  23. memory {
  24. device_type = "memory";
  25. //reg = <0x80000000 0x10000000>; /* 256 MB */
  26. reg = <0x80000000 0x20000000>; /* 512 MB */ /* +++ vern,512MB DDR ,20181030 ---*/
  27. };
  28. vbat: fixedregulator@0 {
  29. compatible = "regulator-fixed";
  30. regulator-name = "vbat";
  31. regulator-min-microvolt = <5000000>;
  32. regulator-max-microvolt = <5000000>;
  33. regulator-boot-on;
  34. };
  35. lis3_reg: fixedregulator@1 {
  36. compatible = "regulator-fixed";
  37. regulator-name = "lis3_reg";
  38. regulator-boot-on;
  39. };
  40. wlan_en_reg: fixedregulator@2 {
  41. compatible = "regulator-fixed";
  42. regulator-name = "wlan-en-regulator";
  43. regulator-min-microvolt = <1800000>;
  44. regulator-max-microvolt = <1800000>;
  45. /* WLAN_EN GPIO for this board - Bank1, pin16 */
  46. gpio = <&gpio1 16 0>;
  47. /* WLAN card specific delay */
  48. startup-delay-us = <70000>;
  49. enable-active-high;
  50. };
  51. matrix_keypad: matrix_keypad@0 {
  52. compatible = "gpio-matrix-keypad";
  53. debounce-delay-ms = <5>;
  54. col-scan-delay-us = <2>;
  55. row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
  56. &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
  57. &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
  58. col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
  59. &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
  60. linux,keymap = <0x0000008b /* MENU */
  61. 0x0100009e /* BACK */
  62. 0x02000069 /* LEFT */
  63. 0x0001006a /* RIGHT */
  64. 0x0101001c /* ENTER */
  65. 0x0201006c>; /* DOWN */
  66. };
  67. gpio_keys: volume_keys@0 {
  68. compatible = "gpio-keys";
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71. autorepeat;
  72. switch@9 {
  73. label = "volume-up";
  74. linux,code = <115>;
  75. gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  76. gpio-key,wakeup;
  77. };
  78. switch@10 {
  79. label = "volume-down";
  80. linux,code = <114>;
  81. gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
  82. gpio-key,wakeup;
  83. };
  84. };
  85. backlight {
  86. compatible = "pwm-backlight";
  87. pwms = <&ecap0 0 50000 0>;
  88. brightness-levels = <0 51 53 56 62 75 101 152 255>;
  89. default-brightness-level = <8>;
  90. };
  91. panel {
  92. compatible = "ti,tilcdc,panel";
  93. status = "okay";
  94. pinctrl-names = "default";
  95. pinctrl-0 = <&lcd_pins_s0>;
  96. panel-info {
  97. ac-bias = <255>;
  98. ac-bias-intrpt = <0>;
  99. dma-burst-sz = <16>;
  100. bpp = <32>;
  101. fdd = <0x80>;
  102. sync-edge = <0>;
  103. sync-ctrl = <1>;
  104. raster-order = <0>;
  105. fifo-th = <0>;
  106. };
  107. display-timings {
  108. 800x480p62 {
  109. clock-frequency = <30000000>;
  110. hactive = <800>;
  111. vactive = <480>;
  112. hfront-porch = <39>;
  113. hback-porch = <39>;
  114. hsync-len = <47>;
  115. vback-porch = <29>;
  116. vfront-porch = <13>;
  117. vsync-len = <2>;
  118. hsync-active = <1>;
  119. vsync-active = <1>;
  120. };
  121. };
  122. };
  123. sound {
  124. compatible = "ti,da830-evm-audio";
  125. ti,model = "AM335x-EVM";
  126. ti,audio-codec = <&tlv320aic3106>;
  127. ti,mcasp-controller = <&mcasp1>;
  128. ti,codec-clock-rate = <12000000>;
  129. ti,audio-routing =
  130. "Headphone Jack", "HPLOUT",
  131. "Headphone Jack", "HPROUT",
  132. "LINE1L", "Line In",
  133. "LINE1R", "Line In";
  134. };
  135. };
  136. &am33xx_pinmux {
  137. pinctrl-names = "default";
  138. pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
  139. matrix_keypad_s0: matrix_keypad_s0 {
  140. pinctrl-single,pins = <
  141. 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
  142. 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
  143. 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
  144. 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
  145. 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
  146. >;
  147. };
  148. volume_keys_s0: volume_keys_s0 {
  149. pinctrl-single,pins = <
  150. 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
  151. 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
  152. >;
  153. };
  154. i2c0_pins: pinmux_i2c0_pins {
  155. pinctrl-single,pins = <
  156. 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
  157. 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
  158. >;
  159. };
  160. i2c1_pins: pinmux_i2c1_pins {
  161. pinctrl-single,pins = <
  162. 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
  163. 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
  164. >;
  165. };
  166. uart0_pins: pinmux_uart0_pins {
  167. pinctrl-single,pins = <
  168. 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
  169. 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
  170. >;
  171. };
  172. uart1_pins: pinmux_uart1_pins {
  173. pinctrl-single,pins = <
  174. 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
  175. 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
  176. 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
  177. 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
  178. >;
  179. };
  180. clkout2_pin: pinmux_clkout2_pin {
  181. pinctrl-single,pins = <
  182. 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
  183. >;
  184. };
  185. nandflash_pins_s0: nandflash_pins_s0 {
  186. pinctrl-single,pins = <
  187. 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
  188. 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
  189. 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
  190. 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
  191. 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
  192. 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
  193. 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
  194. 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
  195. 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
  196. 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
  197. 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
  198. 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
  199. 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
  200. 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
  201. 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
  202. >;
  203. };
  204. ecap0_pins: backlight_pins {
  205. pinctrl-single,pins = <
  206. 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
  207. >;
  208. };
  209. cpsw_default: cpsw_default {
  210. pinctrl-single,pins = <
  211. /* Slave 1 */
  212. 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* MII1_RX_ER.gmii1_rxerr */
  213. 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
  214. 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_txclk.mii1_txclk */
  215. 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
  216. 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxd3.rgmii1_rd3 */
  217. 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxd2.rgmii1_rd2 */
  218. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxd1.rgmii1_rd1 */
  219. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_rxd0.rgmii1_rd0 */
  220. 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
  221. 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.rgmii1_td3 */
  222. 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.rgmii1_td2 */
  223. 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.rgmii1_td1 */
  224. 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.rgmii1_td0 */
  225. >;
  226. };
  227. cpsw_sleep: cpsw_sleep {
  228. pinctrl-single,pins = <
  229. /* Slave 1 reset value */
  230. 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* MII1_RX_ER.gmii1_rxerr */
  231. //0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* MII1_COL.gmii1_col */
  232. //0x10C (PIN_INPUT_PULLDOWN | MUX_MODE7) /* MII1_CRS.gmii1_crs */
  233. 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  234. 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  235. 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  236. 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  237. 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  238. 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  239. 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  240. 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  241. 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  242. 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  243. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  244. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  245. >;
  246. };
  247. davinci_mdio_default: davinci_mdio_default {
  248. pinctrl-single,pins = <
  249. /* MDIO */
  250. 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
  251. 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
  252. >;
  253. };
  254. davinci_mdio_sleep: davinci_mdio_sleep {
  255. pinctrl-single,pins = <
  256. /* MDIO reset value */
  257. 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  258. 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  259. >;
  260. };
  261. #if 0
  262. mmc1_pins: pinmux_mmc1_pins {
  263. pinctrl-single,pins = <
  264. 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
  265. >;
  266. };
  267. #endif
  268. mmc1_pins_default: pinmux_mmc1_pins {
  269. pinctrl-single,pins = <
  270. 0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
  271. 0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
  272. 0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
  273. 0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
  274. 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
  275. 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
  276. /*0x0A8 (PIN_INPUT | MUX_MODE7)*/ /* LCD_DATA2.GPIO2_8 */
  277. 0x08C (PIN_INPUT | MUX_MODE7) /* GPMC_CLK.GPIO2_1 */
  278. >;
  279. };
  280. mmc3_pins: pinmux_mmc3_pins {
  281. pinctrl-single,pins = <
  282. 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
  283. 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
  284. 0x4C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
  285. 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
  286. 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
  287. 0x8C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
  288. >;
  289. };
  290. wlan_pins: pinmux_wlan_pins {
  291. pinctrl-single,pins = <
  292. 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */
  293. 0x19C (PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
  294. 0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
  295. >;
  296. };
  297. lcd_pins_s0: lcd_pins_s0 {
  298. pinctrl-single,pins = <
  299. 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
  300. 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
  301. 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
  302. 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
  303. 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
  304. 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
  305. 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
  306. 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
  307. 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
  308. 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
  309. 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
  310. 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
  311. 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
  312. 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
  313. 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
  314. 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
  315. 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
  316. 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
  317. 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
  318. 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
  319. 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
  320. 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
  321. 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
  322. 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
  323. 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
  324. 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
  325. 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
  326. 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
  327. >;
  328. };
  329. #if 0
  330. am335x_evm_audio_pins: am335x_evm_audio_pins {
  331. pinctrl-single,pins = <
  332. 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
  333. 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
  334. 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
  335. 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
  336. >;
  337. };
  338. #endif
  339. dcan1_pins_default: dcan1_pins_default {
  340. pinctrl-single,pins = <
  341. 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
  342. 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
  343. >;
  344. };
  345. };
  346. &uart0 {
  347. pinctrl-names = "default";
  348. pinctrl-0 = <&uart0_pins>;
  349. status = "okay";
  350. };
  351. &uart1 {
  352. pinctrl-names = "default";
  353. pinctrl-0 = <&uart1_pins>;
  354. status = "okay";
  355. };
  356. &i2c0 {
  357. pinctrl-names = "default";
  358. pinctrl-0 = <&i2c0_pins>;
  359. status = "okay";
  360. clock-frequency = <400000>;
  361. tps: tps@2d {
  362. reg = <0x2d>;
  363. };
  364. };
  365. &usb {
  366. status = "okay";
  367. };
  368. &usb_ctrl_mod {
  369. status = "okay";
  370. };
  371. &usb0_phy {
  372. status = "okay";
  373. };
  374. &usb1_phy {
  375. status = "okay";
  376. };
  377. &usb0 {
  378. status = "okay";
  379. };
  380. &usb1 {
  381. status = "okay";
  382. dr_mode = "host";
  383. };
  384. &cppi41dma {
  385. status = "okay";
  386. };
  387. &i2c1 {
  388. pinctrl-names = "default";
  389. pinctrl-0 = <&i2c1_pins>;
  390. status = "okay";
  391. clock-frequency = <100000>;
  392. lis331dlh: lis331dlh@18 {
  393. compatible = "st,lis331dlh", "st,lis3lv02d";
  394. reg = <0x18>;
  395. Vdd-supply = <&lis3_reg>;
  396. Vdd_IO-supply = <&lis3_reg>;
  397. st,click-single-x;
  398. st,click-single-y;
  399. st,click-single-z;
  400. st,click-thresh-x = <10>;
  401. st,click-thresh-y = <10>;
  402. st,click-thresh-z = <10>;
  403. st,irq1-click;
  404. st,irq2-click;
  405. st,wakeup-x-lo;
  406. st,wakeup-x-hi;
  407. st,wakeup-y-lo;
  408. st,wakeup-y-hi;
  409. st,wakeup-z-lo;
  410. st,wakeup-z-hi;
  411. st,min-limit-x = <120>;
  412. st,min-limit-y = <120>;
  413. st,min-limit-z = <140>;
  414. st,max-limit-x = <550>;
  415. st,max-limit-y = <550>;
  416. st,max-limit-z = <750>;
  417. };
  418. tsl2550: tsl2550@39 {
  419. compatible = "taos,tsl2550";
  420. reg = <0x39>;
  421. };
  422. tmp275: tmp275@48 {
  423. compatible = "ti,tmp275";
  424. reg = <0x48>;
  425. };
  426. tlv320aic3106: tlv320aic3106@1b {
  427. compatible = "ti,tlv320aic3106";
  428. reg = <0x1b>;
  429. status = "okay";
  430. /* Regulators */
  431. AVDD-supply = <&vaux2_reg>;
  432. IOVDD-supply = <&vaux2_reg>;
  433. DRVDD-supply = <&vaux2_reg>;
  434. DVDD-supply = <&vbat>;
  435. };
  436. };
  437. &lcdc {
  438. status = "okay";
  439. };
  440. &elm {
  441. status = "okay";
  442. };
  443. &epwmss0 {
  444. status = "okay";
  445. ecap0: ecap@48300100 {
  446. status = "okay";
  447. pinctrl-names = "default";
  448. pinctrl-0 = <&ecap0_pins>;
  449. };
  450. };
  451. &gpmc {
  452. status = "okay";
  453. pinctrl-names = "default";
  454. pinctrl-0 = <&nandflash_pins_s0>;
  455. /*ranges = <0 0 0x08000000 0x1000000>;*/ /* CS0: 16MB for NAND */
  456. ranges = <0 0 0x08000000 0x80000000>; /*+++ vern,NAND,20181030 ---*/
  457. nand@0,0 {
  458. reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  459. ti,nand-ecc-opt = "bch16";
  460. ti,elm-id = <&elm>;
  461. nand-bus-width = <8>;
  462. gpmc,device-width = <1>;
  463. gpmc,sync-clk-ps = <0>;
  464. gpmc,cs-on-ns = <0>;
  465. gpmc,cs-rd-off-ns = <44>;
  466. gpmc,cs-wr-off-ns = <44>;
  467. gpmc,adv-on-ns = <6>;
  468. gpmc,adv-rd-off-ns = <34>;
  469. gpmc,adv-wr-off-ns = <44>;
  470. gpmc,we-on-ns = <0>;
  471. gpmc,we-off-ns = <40>;
  472. gpmc,oe-on-ns = <0>;
  473. gpmc,oe-off-ns = <54>;
  474. gpmc,access-ns = <64>;
  475. gpmc,rd-cycle-ns = <82>;
  476. gpmc,wr-cycle-ns = <82>;
  477. gpmc,wait-on-read = "true";
  478. gpmc,wait-on-write = "true";
  479. gpmc,bus-turnaround-ns = <0>;
  480. gpmc,cycle2cycle-delay-ns = <0>;
  481. gpmc,clk-activation-ns = <0>;
  482. gpmc,wait-monitoring-ns = <0>;
  483. gpmc,wr-access-ns = <40>;
  484. gpmc,wr-data-mux-bus-ns = <0>;
  485. /* MTD partition table */
  486. /* All SPL-* partitions are sized to minimal length
  487. * which can be independently programmable. For
  488. * NAND flash this is equal to size of erase-block */
  489. #address-cells = <1>;
  490. #size-cells = <1>;
  491. partition@0 {
  492. label = "SPL";
  493. reg = <0x00000000 0x00080000>;
  494. };
  495. partition@1 {
  496. label = "Primary u-boot";
  497. reg = <0x00080000 0x00100000>;
  498. };
  499. partition@2 {
  500. label = "u-boot-env";
  501. reg = <0x00180000 0x00080000>;
  502. };
  503. partition@3 {
  504. label = "Secondary u-boot";
  505. reg = <0x00200000 0x00100000>;
  506. };
  507. partition@4 {
  508. label = "Primary dtb";
  509. reg = <0x00300000 0x00080000>;
  510. };
  511. partition@5 {
  512. label = "Secondary dtb";
  513. reg = <0x00380000 0x00080000>;
  514. };
  515. partition@6 {
  516. label = "Primary kernel";
  517. reg = <0x00400000 0x00A00000>;
  518. };
  519. partition@7 {
  520. label = "Secondary kernel";
  521. reg = <0x00E00000 0x00A00000>;
  522. };
  523. partition@8 {
  524. label = "Primary rootfs";
  525. reg = <0x03000000 0x03000000>;
  526. };
  527. partition@9 {
  528. label = "Secondary rootfs";
  529. reg = <0x06000000 0x03000000>;
  530. };
  531. partition@10 {
  532. label = "Primary user configuration";
  533. reg = <0x09000000 0x00600000>;
  534. };
  535. partition@11 {
  536. label = "Secondary user configuration";
  537. reg = <0x09600000 0x00600000>;
  538. };
  539. partition@12 {
  540. label = "Factory default configuration";
  541. reg = <0x09C00000 0x00600000>;
  542. };
  543. partition@13 {
  544. label = "Storage";
  545. reg = <0x0A200000 0x75E00000>;
  546. };
  547. };
  548. };
  549. #include "tps65910.dtsi"
  550. #if 0
  551. &mcasp1 {
  552. pinctrl-names = "default";
  553. pinctrl-0 = <&am335x_evm_audio_pins>;
  554. status = "okay";
  555. op-mode = <0>; /* MCASP_IIS_MODE */
  556. tdm-slots = <2>;
  557. /* 4 serializers */
  558. serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
  559. 0 0 1 2
  560. >;
  561. tx-num-evt = <32>;
  562. rx-num-evt = <32>;
  563. };
  564. #endif
  565. &tps {
  566. vcc1-supply = <&vbat>;
  567. vcc2-supply = <&vbat>;
  568. vcc3-supply = <&vbat>;
  569. vcc4-supply = <&vbat>;
  570. vcc5-supply = <&vbat>;
  571. vcc6-supply = <&vbat>;
  572. vcc7-supply = <&vbat>;
  573. vccio-supply = <&vbat>;
  574. regulators {
  575. vrtc_reg: regulator@0 {
  576. regulator-always-on;
  577. };
  578. vio_reg: regulator@1 {
  579. regulator-always-on;
  580. };
  581. vdd1_reg: regulator@2 {
  582. /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
  583. regulator-name = "vdd_mpu";
  584. regulator-min-microvolt = <912500>;
  585. regulator-max-microvolt = <1312500>;
  586. regulator-boot-on;
  587. regulator-always-on;
  588. };
  589. vdd2_reg: regulator@3 {
  590. /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
  591. regulator-name = "vdd_core";
  592. regulator-min-microvolt = <912500>;
  593. regulator-max-microvolt = <1150000>;
  594. regulator-boot-on;
  595. regulator-always-on;
  596. };
  597. vdd3_reg: regulator@4 {
  598. regulator-always-on;
  599. };
  600. vdig1_reg: regulator@5 {
  601. regulator-always-on;
  602. };
  603. vdig2_reg: regulator@6 {
  604. regulator-always-on;
  605. };
  606. vpll_reg: regulator@7 {
  607. regulator-always-on;
  608. };
  609. vdac_reg: regulator@8 {
  610. regulator-always-on;
  611. };
  612. vaux1_reg: regulator@9 {
  613. regulator-always-on;
  614. };
  615. vaux2_reg: regulator@10 {
  616. regulator-always-on;
  617. };
  618. vaux33_reg: regulator@11 {
  619. regulator-always-on;
  620. };
  621. vmmc_reg: regulator@12 {
  622. regulator-min-microvolt = <1800000>;
  623. regulator-max-microvolt = <3300000>;
  624. regulator-always-on;
  625. };
  626. };
  627. };
  628. &mac {
  629. pinctrl-names = "default", "sleep";
  630. pinctrl-0 = <&cpsw_default>;
  631. pinctrl-1 = <&cpsw_sleep>;
  632. status = "okay";
  633. };
  634. &davinci_mdio {
  635. pinctrl-names = "default", "sleep";
  636. pinctrl-0 = <&davinci_mdio_default>;
  637. pinctrl-1 = <&davinci_mdio_sleep>;
  638. status = "okay";
  639. };
  640. &cpsw_emac0 {
  641. phy_id = <&davinci_mdio>, <1>;
  642. phy-mode = "mii";
  643. };
  644. &cpsw_emac1 {
  645. phy_id = <&davinci_mdio>, <2>;
  646. phy-mode = "mii";
  647. };
  648. &tscadc {
  649. status = "okay";
  650. tsc {
  651. ti,wires = <4>;
  652. ti,x-plate-resistance = <200>;
  653. ti,coordinate-readouts = <5>;
  654. ti,wire-config = <0x00 0x11 0x22 0x33>;
  655. ti,charge-delay = <0x400>;
  656. };
  657. adc {
  658. ti,adc-channels = <4 5 6 7>;
  659. };
  660. };
  661. &mmc1 {
  662. status = "okay";
  663. vmmc-supply = <&vmmc_reg>;
  664. bus-width = <4>;
  665. pinctrl-names = "default";
  666. pinctrl-0 = <&mmc1_pins_default>;
  667. cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  668. };
  669. &mmc3 {
  670. /* these are on the crossbar and are outlined in the
  671. xbar-event-map element */
  672. dmas = <&edma 12
  673. &edma 13>;
  674. dma-names = "tx", "rx";
  675. status = "okay";
  676. vmmc-supply = <&wlan_en_reg>;
  677. bus-width = <4>;
  678. pinctrl-names = "default";
  679. pinctrl-0 = <&mmc3_pins &wlan_pins>;
  680. ti,non-removable;
  681. ti,needs-special-hs-handling;
  682. cap-power-off-card;
  683. keep-power-in-suspend;
  684. #address-cells = <1>;
  685. #size-cells = <0>;
  686. wlcore: wlcore@0 {
  687. compatible = "ti,wl1835";
  688. reg = <2>;
  689. interrupt-parent = <&gpio3>;
  690. interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
  691. };
  692. };
  693. &edma {
  694. ti,edma-xbar-event-map = /bits/ 16 <1 12
  695. 2 13>;
  696. };
  697. &sham {
  698. status = "okay";
  699. };
  700. &aes {
  701. status = "okay";
  702. };
  703. &dcan1 {
  704. status = "disabled"; /* Enable only if Profile 1 is selected */
  705. pinctrl-names = "default";
  706. pinctrl-0 = <&dcan1_pins_default>;
  707. };